DSPIC30F6013T-20I/PF【PDF 45/228 页】IC DSPIC MCU/DSP 132K 80TQFP

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2006 Microchip Technology Inc.

DS70117F-page 137

dsPIC30F6011/6012/6013/6014

19.4

Programming the Start of

Conversion Trigger

The conversion trigger will terminate acquisition and

start the requested conversions.

The SSRC<2:0> bits select the source of the conver-

sion trigger. The SSRC bits provide for up to 4 alternate

sources of conversion trigger.

When SSRC<2:0> = 000, the conversion trigger is

under software control. Clearing the SAMP bit will

cause the conversion trigger.

When SSRC<2:0> = 111 (Auto-Start mode), the con-

version trigger is under A/D clock control. The SAMC

bits select the number of A/D clocks between the start

of acquisition and the start of conversion. This provides

the fastest conversion rates on multiple channels.

SAMC must always be at least 1 clock cycle.

Other trigger sources can come from timer modules or

external interrupts.

19.5

Aborting a Conversion

Clearing the ADON bit during a conversion will abort

the current conversion and stop the sampling sequenc-

ing until the next sampling trigger. The ADCBUF will not

be updated with the partially completed A/D conversion

sample. That is, the ADCBUF will continue to contain

the value of the last completed conversion (or the last

value written to the ADCBUF register).

If the clearing of the ADON bit coincides with an auto-

start, the clearing has a higher priority and a new

conversion will not start.

19.6

Selecting the ADC Conversion

Clock

The ADC conversion requires 14 TAD. The source of

the ADC conversion clock is software selected, using a

six-bit counter. There are 64 possible options for TAD.

EQUATION 19-1:

ADC CONVERSION

CLOCK

The internal RC oscillator is selected by setting the

ADRC bit.

For correct ADC conversions, the ADC conversion

clock (TAD) must be selected to ensure a minimum TAD

time of 334 nsec (for VDD = 5V). Refer to the Electrical

Specifications section for minimum TAD under other

operating conditions.

Example 19-1 shows a sample calculation for the

ADCS<5:0> bits, assuming a device operating speed

of 30 MIPS.

EXAMPLE 19-1:

ADC CONVERSION

CLOCK AND SAMPLING

RATE CALCULATION

TAD = TCY * (0.5 * (ADCS<5:0> + 1))

Minimum TAD = 334 nsec

ADCS<5:0> = 2

– 1

TAD

TCY

TCY = 33 .33 nsec (30 MIPS)

= 2

– 1

334 nsec

33.33 nsec

= 19.04

Therefore,

Set ADCS<5:0> = 19

Actual TAD =

(ADCS<5:0> + 1)

TCY

(19 + 1)

33.33 nsec

= 334 nsec

If SSRC<2:0> = ‘111’ and SAMC<4:0> = ‘00001’

Since,

Sampling Time = Acquisition Time + Conversion Time

= 1 TAD + 14 TAD

= 15 x 334 nsec

Therefore,

Sampling Rate =

= ~200 kHz

(15 x 334 nsec)

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